1. Field of the Invention
This invention relates to an electro-luminescence display (ELD), and more particularly to an electro-luminescence display device and a driving method thereof wherein pixel cells are pre-charged by a voltage to thereby display a picture having a desired gray level.
2. Description of the Related Art
Recently, various flat panel display devices with reduced weight and bulk have been developed that eliminate various disadvantages of displays employing cathode ray tubes (CRT). Such flat panel display devices include liquid crystal displays (LCD), field emission displays (FED), plasma display panels (PDP) and electro-luminescence (EL) displays, etc.
The EL display is a self-luminous device capable of causing a phosphorous material to emit light by a re-combination of electrons with holes. There are two types of EL displays depending upon the material and structure used: inorganic and organic. The EL display has the advantage of a CRT in that it has a faster response speed than a passive-type light-emitting device requiring a separate light source like the LCD.
FIG. 1 is a sectional view of a related art organic EL structure to explain the light-emitting principles of the EL display device.
Referring to FIG. 1, the organic EL device of the EL display (ELD) includes an electron injection layer 4, an electron carrier layer 6, a light-emitting layer 8, a hole carrier layer 10′ and a hole injection layer 12 that are sequentially disposed between a cathode 2 and an anode 14.
If a voltage is applied between the anode 14, which may be a transparent electrode and the cathode 2, which may be a metal electrode, then electrons produced at the cathode 2 are moved, via the electron injection layer 4 and the electron carrier layer 6, into the light-emitting layer 8, while holes produced at the anode 14 are moved, via the hole injection layer 12 and the hole carrier layer 10, into the light-emitting layer 10. Thus, the electrons and the holes fed from the electron carrier layer 6 and the hole carrier layer 10 collide at the light-emitting layer and recombine to emit light via the transparent electrode (i.e., the anode 14) to thereby display an image.
FIG. 2 shows a related art active matrix type EL display device.
Referring to FIG. 2, the related art active matrix type EL display device includes an EL display panel 16 with pixel (PE) cells 22 arranged at each crossing between gate electrode lines GL and data electrode lines DL, a gate driver 18 that drives the gate electrode lines GL, a data driver 20 that drives the data electrode lines DL, and a timing controller 24 that controls the gate driver 18 and the data driver 20.
The timing controller 24 controls the data driver 20 and the gate driver 18. The timing controller 24 applies various control signals to the data driver 20 and the gate driver 18. Further, the timing controller 24 re-aligns data and supplies the aligned data to the data driver 20.
The gate driver 18 sequentially applies a gate signal to the gate electrode lines GL under the control of the timing controller 24.
The data driver 20 applies video signals to the data electrode lines DL under the control of the timing controller 24. The data driver 20 applies one horizontal line of a video signal at a time to the data electrode lines DL once every horizontal synchronization period (H) when a gate signal is applied.
The PE cells 22 generate light corresponding to the video signals (i.e., current signals) applied to the data electrode lines DL to thereby display an image corresponding to the video signals. As shown in FIG. 3, each PE cell 22 includes a light-emitting cell driving circuit 30 to drive a light-emitting cell organic light emitting diode (OLED) in response to a driving signal supplied from each of the data electrode lines DL and the gate electrode lines GL, and a light-emitting cell OLED connected between the light-emitting cell driving circuit 30 and the ground voltage source GND.
The light-emitting cell driving circuit 30 includes a first driving thin film transistor (TFT) T1 connected between the supply voltage line VDD and the light-emitting cell OELD, a first switching TFT T3 connected between the gate electrode line and the data electrode line DL, a second driving TFT T2 connected between the first switching TFT T3 and the supply voltage line VDD to form a current mirror circuit with respect to the driving TFT T1, a second switching TFT T4 connected between the gate electrode line GL and the second driving TFT T2, and a storage capacitor Cst connected between a node positioned between the first and second driving TFTs T1 and T2 and the supply voltage line VDD. By way of example, the TFTs are a p-type electron metal-oxide semiconductor field effect transistor (MOSFET).
A gate terminal of the first driving TFT T1 is connected to the gate terminal of the second driving TFT T2; a source terminal thereof is connected to the supply voltage line VDD; and a drain terminal thereof is connected to the light-emitting cell OLED. A source terminal of the second driving TFT T2 is connected to the supply voltage line VDD, and a drain terminal thereof is connected to a drain terminal of the first switching TFT T3 and a source terminal of the second switching TFT T4.
A source terminal of the first switching TFT T3 is connected to the data electrode line DL, and a gate terminal thereof is connected to the gate electrode line GL. A drain terminal of the second switching TFT T4 is connected to the gate terminals of the first and second driving TFTs T1 and T2 and the storage capacitor Cst. A gate terminal of the second switching TFT T4 is connected to the gate electrode line GL.
Herein, the first and second driving TFTs T1 and T2 are connected to each other in such a manner to form a current mirror. Thus, assuming that the first and second driving TFTs T1 and T2 have the same channel width, a current flowing in the first driving TFT T1 is set to be equal to a current flowing in the second driving TFT T2.
The operation of the light-emitting cell driving circuit 30 will be described below.
First, a gate signal is applied from the gate electrode line GL to a group of PE cells 22 along a horizontal line. When the gate signal is applied, the first and second switching TFTs T3 and T4 are turned on. When the first and second switching TFTs T3 and T4 are turned on, a video signal from the data electrode line DL is applied, via the first and second switching TFTs T3 and T4, to the gate terminals of the first and second driving TFTs T1 and T2. The first and second driving TFTs T1 and T2 supplied with the video signal are turned on. Herein, the first driving TFT T1 controls a current flowing from its source terminal (i.e., VDD) into its drain terminal in response to the video signal applied to its gate terminal to apply this current to the light-emitting cell OLED, thereby resulting in the light-emitting cell OLED emitting light having a brightness corresponding to the video signal.
At the same time, the second driving TFT T2 applies a current id fed from the supply voltage line VDD, via the first switching TFT T3, to the data electrode line DL. Because the first and second driving TFTs T1 and T2 form a current mirror circuit, the same current flows in the first and second driving TFTs T1 and T2. Meanwhile, the storage capacitor Cst stores a voltage from the supply voltage line VDD corresponding to the current id flowing into the second driving TFT T2. Further, the storage capacitor Cst turns on the first driving TFT T1 using a voltage stored therein when the gate signal becomes an OFF signal to turn off the first and second switching TFTs T3 and T4, thereby applying a current corresponding to the video signal to the light-emitting cell OEL.
Herein, the related art driver 20 applies a desired current to the PE cell 22 in correspondence with data from the timing controller 24. In other words, the related art data driver 20 drives the PE cells 22.
The related art data driver 20 includes a plurality of data driving integrated circuits (IC's), each of which is configured as shown in FIG. 4.
Referring to FIG. 4, the data driver 20 includes a shift register 40, a first latch 42, a second latch 44 and a current driver 46.
The shift register 40 sequentially shifts a source start pulse SSP from the timing controller 24 in response to a source sampling clock SSC to thereby output a sampling signal.
The first latch 42 sequentially samples data from the timing controller 24 for each data line in response to the sampling signal from the shift register 40 and latches the sampled data. The first latch 42 includes i latches (wherein i is an integer corresponding to the number of data lines) for latching i image data, each of which has a certain number of data bits. The image data stored in the first latch 42 is then supplied to the second latch 44.
The second latch 44 temporarily stores the image data from the first latch 42 and simultaneously outputs the stored image data in response to a source output enable signal SOE from the timing controller 24.
The current driver 46 produces a current to be applied to the PE cell 22 corresponding to the data received from the second latch 44. This will be described with reference to FIG. 5. The current driver 46 includes i current driving blocks 48 for each data line. The current driving block 48 receives data from the second latch 44 and produces a current id corresponding to the data using a gamma current signal corresponding to the received data. Thus, a current id corresponding to a desired video signal is applied to each of the data lines DL, thereby displaying a desired image corresponding to the image data.
As described above, the related art EL display device drives the PE cell 22 only with a current. However, if the PE cell 22 is driven only with a current, then a problem arises in that certain desired gray levels are unable to be displayed. In other words, the conventional EL display device supplies a current value changing in increments on the order of about a μA in correspondence with a data. For instance, the data driving IC allows a current of 1 μA to flow at a gray level 1 while allowing a current of 2 μA to flow at a gray level 2. However, if such a current value that changes at a μA level is applied during one horizontal period (H), then a voltage corresponding to the current fails to be charged in the storage capacitor Cst. In other words, the storage capacitor Cst fails to be charged with a voltage corresponding to the current within a limited time (H) because the PE cell 22 is driven only with a current, and hence a problem arises in that a desired gray level of picture fails to be displayed.